1. Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of fabricating dual-metal trabsistors having different work functions in the fabrication of integrated circuits.
2. Description of the Prior Art
It is anticipated that a single metal gate with mid-gap work function values will not be suitable for CMOS applications due to buried channel effects. By using a single metal gate for both NMOSFET and PMOSFET, the threshold voltage becomes too high for both types of transistors. In order to achieve a lower threshold voltage, additional implantation is required and this will result in buried channel effects. The short channel effect control will then be degraded. However, with dual metal gates having different work functions, additional implantation is not required. That is, one electrode with a lower work function will be used in the NMOSFET while another electrode with a higher work function will be used for the PMOSFET. That means that the threshold voltage for NMOSFET and PMOSFET can be tailored independently. It is desired to maintain the conventional CMOS process flow in the dual metal gate process.
U.S. Pat. No. 6,043,157 to Gardner et al shows a process for forming dual gates where one gate is polysilicon and the other gate is metal. U.S. Pat. No. 5,960,270 to Misra et al discloses a process wherein the same mid-gap work function metal is used for both n- and p-gates. U.S. Pat. No. 6,083,836 to Rodder teaches a dummy gate process where two gates are formed. For example, one gate is polysilicon and the other is aluminum. U.S. Pat. No. 6,051,487 to Gardner et al teaches a dummy gate process using a polysilicon or a metal gate.
Accordingly, a primary object of the invention is to provide a process for forming dual metal gates for CMOS transistors in the fabrication of integrated circuits.
A further object of the invention is to provide a process for forming dual-metal gate CMOS transistors having different work functions in the fabrication of integrated circuits.
Another object of the invention is to provide a process for forming dual-metal gate CMOS transistors where one gate comprises a metal and the other gate comprises the metal""s silicide.
Yet another object of the invention is to provide a process for forming dual-metal gate CMOS transistors comprising a metal and the metal silicide.
A still further object of the invention is to provide a process for forming dual-metal gate CMOS transistors comprising a first metal silicide and a second metal silicide wherein the metal is the same in both gates and the silicide concentration is different.
In accordance with the objects of the invention, a method for forming dual-metal gate CMOS transistors is achieved. First and second active areas of a semiconductor substrate are separated by isolation regions. One of the active areas will be PMOS and the other will be NMOS. A gate dielectric layer is formed overlying the semiconductor substrate in each of the active areas. A metal layer is deposited overlying the gate dielectric layer. Silicon ions are implanted into the metal layer in the PMOS area to form an implanted metal layer and the implanted metal layer is silicided to form a metal silicide layer. Thereafter, the metal layer and the metal silicide layer are patterned to form a metal gate in a first active area and a metal silicide gate in a second active area to complete formation of dual-metal gate CMOS transistors in the fabrication of an integrated circuit. The metal silicide may have a higher or lower work function depending on the metal used. The PMOS gate will be formed from the gate having the higher work function.
Also, in accordance with the objects of the invention, a second method for forming dual-metal gate CMOS transistors is achieved. First and second active areas of a semiconductor substrate are separated by isolation regions. One of the active areas will be PMOS and the other will be NMOS. A dummy gate is formed in each of the active areas. The dummy gates are covered with a dielectric layer which is planarized whereby a top surface of each of the dummy gates is exposed. The exposed dummy gates are removed, leaving gate openings to the semiconductor substrate. A gate dielectric layer is formed overlying the semiconductor substrate in each of the gate openings. A metal layer is deposited within the gate openings to form metal gates. Silicon ions are implanted into the metal gate only in a first active area to form an implanted metal gate. The implanted metal gate is silicided to form a metal silicide gate in the first active area to complete formation of dual-metal gate CMOS transistors in the fabrication of an integrated circuit. The metal silicide may have a higher or lower work function depending on the metal used. The PMOS gate will be formed from the gate having the higher work function.
Also, in accordance with the objects of the invention, a third method for forming dual-metal gate CMOS transistors is achieved. First and second active areas of a semiconductor substrate are separated by isolation regions. One of the active areas will be PMOS and the other will be NMOS. A gate dielectric layer is formed overlying the semiconductor substrate in each of the active areas. A metal layer is deposited overlying the gate dielectric layer. First silicon ions are implanted into the metal layer in a first active area to form an implanted metal layer and the implanted metal layer is silicided to form a first metal silicide layer. Second silicon ions are implanted into the metal layer in the second active area to form an implanted metal layer and the implanted metal layer is silicided to form a second metal silicide layer wherein the silicon concentration in the second metal silicide layer is higher than the silicon concentration in the first metal silicide layer. Thereafter, the first metal silicide layer and the second metal silicide layer are patterned to form a first metal silicide gate in the first area and a second metal silicide gate in the second area to complete formation of dual-metal gate CMOS transistors in the fabrication of an integrated circuit. The PMOS gate will be formed from the gate having the higher work function.
Also, in accordance with the objects of the invention, a fourth method for forming dual-metal gate CMOS transistors is achieved. First and second active areas of a semiconductor substrate are separated by isolation regions. One of the active areas will be PMOS and the other will be NMOS. A dummy gate is formed in each of the active areas. The dummy gates are covered with a dielectric layer which is planarized whereby a top surface of each of the dummy gates is exposed. The exposed dummy gates are removed, leaving gate openings to the semiconductor substrate. A gate dielectric layer is formed overlying the semiconductor substrate in each of the gate openings. A metal layer is deposited within the gate openings to form metal gates. First silicon ions are implanted into the metal gate only in a first active area to form an implanted metal gate. The implanted metal gate is silicided to form a first metal silicide gate in the first active area. Second silicon ions are implanted into the metal gate in the second active area to form an implanted metal gate and the implanted metal gate is silicided to form a second metal silicide gate wherein the silicon concentration in the second metal silicide gate is different from the silicon concentration in the first metal silicide gate to complete formation of dual-metal gate CMOS transistors in the fabrication of an integrated circuit. The PMOS gate will be formed from the gate having the higher work function.
Also, in accordance with the objects of the invention, a dual-metal gate CMOS integrated circuit device is achieved. The device comprises first and second active areas of a semiconductor substrate separated by isolation regions. One of the active areas will be PMOS and the other will be NMOS. A metal gate in the first active area overlies a gate dielectric layer, and a metal silicide gate in the second active area overlies a gate dielectric layer wherein the metal in the metal gate is the same material as the metal in the metal silicide gate. The metal silicide may have a higher or lower work function depending on the metal used. The PMOS gate will be formed from the gate having the higher work function.
Also, in accordance with the objects of the invention, another dual-metal gate CMOS integrated circuit device is achieved. The device comprises first and second active areas of a semiconductor substrate separated by isolation regions. One of the active areas will be PMOS and the other will be NMOS. A first metal silicide gate in the first active area overlies a gate dielectric layer, and a second metal silicide gate in the second active area overlies a gate dielectric layer wherein the metal in the two gates is the same metal and the silicon concentration is different in each of the two gates. The PMOS gate will be formed from the gate having the higher work function.